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HT86030/ht86070 voice synthesizer 8-bit mcu selection table body HT86030 ht86070 voice rom size 768k-bit 1536k-bit voice length 36 sec 72 sec note: * voice length is estimated by 21k-bit data rate rev. 1.00 1 february 20, 2006 features operating voltage: 2.4v~5.2v system clock: 4mhz~8mhz crystal or rc oscillator for system clock 16 i/o pins 8k 16-bit program rom 208 8-bit ram one external interrupt input two 16-bit programmable timer counter and overflow interrupts 12-bit high quality d/a output by transistor or ht82v733 built-in voice rom in various capacity one 8-bit counter with 3-bit prescaler watchdog timer 8-level subroutine nesting halt function and wake-up feature reduce power consumption up to 1 s (0.5 s) instruction cycle with 4mhz (8mhz) system clock support 16-bit table read instruction (tblp, tbhp) 63 powerful and efficient instructions 28-pin sop package applications intelligent educational leisure products alert and warning systems high end leisure product controllers sound effect generators general description the HT86030/ht86070 series are 8-bit high perfor- mance microcontroller with voice synthesizer and tone generator. the HT86030/ht86070 is designed for ap- plications on multiple i/os with sound effects, such as voice and melody. it can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. it has a single built-in high qual - ity, d/a output. there is an external interrupt which can be triggered with falling edge pulse or falling/rising edge pulse. the HT86030/ht86070 is excellent for versatile voice and sound effect product applications. the efficient mcu instructions allow users to program the powerful custom applications. the system frequency of HT86030/ht86070 can be up to 8mhz under 2.4v and include a halt function to reduce power consumption. technical document tools information faqs
block diagram pin assignment HT86030/ht86070 rev. 1.00 2 february 20, 2006

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pad assignment HT86030 chip size: 2180 2095 ( m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86070 chip size: 2180 2500 ( m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. HT86030/ht86070 rev. 1.00 3 february 20, 2006 0 * - . 1 4 6 0 * - . 1 4 6 0 * - ! 1 ! . ! - ! * ! 0 ! ! ! 2 2 2 2 0 2 * 2 - 2 . 2 1 ! ! 7 8 9 ! 0 * - . 1 4 6 0 * - . 1 4 6 0 * - ! 1 ! . ! - ! * ! 0 ! ! ! 2 2 2 2 0 2 * 2 - 2 . 2 1 ! ! 7 8 9 !
pad coordinates HT86030 pad no. x y pad no. x y 1 940.200 3.100 14 444.300 897.100 2 940.200 98.200 15 341.300 897.100 3 940.200 201.200 16 246.200 897.100 4 940.200 296.300 17 255.700 830.550 5 940.200 399.300 18 365.000 796.050 6 940.200 494.400 19 465.000 796.050 7 940.200 597.400 20 565.100 796.050 8 940.200 692.500 21 690.250 828.350 9 935.600 897.100 22 824.350 832.150 10 840.500 897.100 23 927.350 832.150 11 737.500 897.100 24 924.100 618.924 12 642.400 897.100 25 924.100 514.624 13 539.400 897.100 ht86070 pad no. x y pad no. x y 1 940.200 205.600 14 444.300 1099.600 2 940.200 300.700 15 341.300 1099.600 3 940.200 403.700 16 246.200 1099.600 4 940.200 498.800 17 255.700 1033.050 5 940.200 601.800 18 365.000 998.550 6 940.200 696.900 19 465.000 998.550 7 940.200 799.900 20 565.100 998.550 8 940.200 895.000 21 690.250 1030.850 9 935.600 1099.600 22 824.350 1034.650 10 840.500 1099.600 23 927.350 1034.650 11 737.500 1099.600 24 924.100 821.424 12 642.400 1099.600 25 924.100 717.124 13 539.400 1099.600 HT86030/ht86070 rev. 1.00 4 february 20, 2006
pad description pad name i/o mask option description pa0~pa7 i/o wake-up, pull-high or none bidirectional 8-bit i/o port. each bit can be configured as a wake-up input by mask option. software instructions determine the cmos output or schmitt trigger input with or without pull-high resistor (mask option). pb0~pb7 i/o pull-high or none bidirectional 8-bit i/o port. software instructions determine the cmos output or schmitt trigger input (pull-high resistor depending on mask op - tion). vss negative power supply, ground vdd positive power supply vdda dac power supply vssa dac negative power supply, ground res i schmitt trigger reset input, active low int i falling edge trigger or falling/rising edge trigger external interrupt schmitt trigger input without pull-high resistor. choice falling edge trigger or falling/rising edge trigger by mask option. falling edge triggered active on a high to low transition. rising edge triggered active on a low to high transition. osc1 osc2 rc or crystal osc1 and osc2 are connected to an rc network or a crystal (by mask option) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. the system clock may come from the crystal, the two pins cannot be floating. aud o audio output for driving a external transistor or for driving ht82v733 absolute maximum ratings supply voltage ..........................v ss 0.3v to v ss +5.5v storage temperature ........................... 50 cto125 c input voltage .............................v ss 0 . 3v to v dd +0.3v operating temperature .......................... 20 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. HT86030/ht86070 rev. 1.00 5 february 20, 2006
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz/8mhz 2.4 5.2 v i stb1 standby current (watchdog off) 3v no load, system halt 1 a 5v 2 i stb2 standby current(watchdog on) 3v no load, system halt 7 a 5v 10 i dd operating current (rc osc) 3v no load, f sys =8mhz 3.5 ma 5v 8 i ol i/o port sink current 3v v ol =0.1v dd 11 ma 5v 25 i oh i/o port source current 3v v oh =0.9v dd 6 ma 5v 15 i o aud source current 3v v oh =0.9v dd 3 ma 5v 7 v il1 input low voltage for i/o ports 3v 1.3 v 5v 2.3 v ih1 input high voltage for i/o ports 3v 1.8 v 5v 2.9 v il2 reset low voltage (res ) 3v 1.4 v 5v 3 v ih2 reset high voltage (res ) 3v 2.4 v 5v 3.9 r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (rc osc) 2.4v~5.2v 4 8 mhz f sys2 system clock (crystal osc) 2.4v~5.2v 4 8 mhz f timer timer input frequency 2.4v~5.2v 0 8 mhz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t wdt1 watchdog time-out period (wdt osc) 3v without wdt prescaler 11 23 46 ms 5v 8 17 33 ms t wdt2 watchdog time-out period (system clock) without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 t sys t int interrupt pulse width 1 s HT86030/ht86070 rev. 1.00 6 february 20, 2006
characteristics curves HT86030/ht86070 r vs. f characteristics curve HT86030/ht86070 v vs. f characteristics curve HT86030/ht86070 rev. 1.00 7 february 20, 2006 : ; " ' 7 < = 9 4 . * ' 7 > 9 - 4 * 1 0 * ? - 0 : ; " ' 7 < = 9 4 . * ' 7 9 ? * ? 4 0 ? 0 ? . * * ? - * ? 4 - ? 4 < = ) * - > . < = ) 6 > * < = ) 4 > : ; " ' 7 < = 9 4 . * ' 7 9 ? * ? 4 0 ? 0 ? . * * ? - * ? 4 - ? 4 < = ) - - > . < = ) - > * < = ) 6 1 >
HT86030/ht86070 rev. 1.00 8 february 20, 2006 functional description execution flow the system clock for the HT86030/ht86070 series is derived from either a crystal or an rc oscillator. it is in - ternally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute within one cycle. if an instruc - tion changes the program counter, two cycles are required to complete the instruction. program counter pc the 13-bit program counter (pc) controls the sequence in which the instructions stored in program rom are ex - ecuted. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. mode program counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000000 external or serial input interrupt 0000000000100 timer/event counter 0 overflow 0000000001000 timer/event counter 1 overflow 0000000001100 timer counter 3 overflow 0000000010100 skip program counter+2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 program counter note: *12~*0: program counter bits s12~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits 0 * 0 * 0 * :
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HT86030/ht86070 rev. 1.00 9 february 20, 2006 the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is ob - tained. the lower byte of the program counter (pcl) is a read/write register (06h). moving data into the pcl per - forms a short jump. the destination must be within 256 locations. when a control transfer takes place, an additional dummy cycle is required. program memory rom the program memory stores the program instructions that are to be executed. it also includes data, table and interrupt entries, addressed by the program counter along with the table pointer. the program memory size for HT86030/ht86070 is 8192 16 bits. certain loca - tions in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. the program always begins execution at location 000h each time the system is reset. location 004h this area is reserved for the external interrupt service program. if the int input pin is activated, and the inter- rupt is enabled and the stack is not full, the program will jump to location 004h and begins execution. location 008h this area is reserved for the 16-bit timer/event coun - ter 0 interrupt service program. if a timer interrupt re - sults from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram will jump to location 008h and begins execution. location 00ch this area is reserved for the 16-bit timer/event coun - ter 1 interrupt service program. if a timer interrupt re - sults from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram will jump to location 00ch and begins execu - tion. location 014h this area is reserved for the 8-bit timer counter 3 in - terrupt service program. if a timer interrupt results from a timer counter 3 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 014h and begins execution. table location any location in the rom space can be used as look up tables. the instructions tabrdc [m] (used for any bank) and tabrdl [m] (only used for last page of pro - gram rom) transfer the contents of the lower-order byte to the specified data memory [m], and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined. the higher-order bytes of the table word are transferred to the tblh. the table higher-order byte register (tblh) is read only. the table pointer (tbhp, tblp) is a read/write register, which indicates the table location. because tbhp is un- known after power on reset, tbhp must be set speci- fied. stack register stack the stack register is a special part of the memory used to save the contents of the program counter. this stack is organized into eight levels. it is neither part of the data nor part of the program space, and cannot be read or written to. its activated level is indexed by a stack pointer (sp) and cannot be read or written to. at a sub - routine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. instruction table location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111@7@6@5@4@3@2@1@0 table location note: *12~*0: current program rom table @7~@0: write @7~@0 to tblp pointer register p12~p8: write p12~p8 to tbhp pointer register < * < 4 < <
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HT86030/ht86070 rev. 1.00 10 february 20, 2006 the program counter is restored to its previous value from the stack at the end of subroutine or interrupt rou - tine, which is signaled by return instruction (ret or reti). after a chip resets, sp will point to the top of the stack. the interrupt request flag will be recorded but the ac - knowledgment will be inhibited when the stack is full and a non-masked interrupt takes place. after the stack pointer is decremented (by ret or reti), the interrupt request will be serviced. this feature prevents stack overflow and allows programmers to use the structure more easily. in a similar case, if the stack is full and a call is subsequently executed, stack overflow oc - curs and the first entry is lost. data memory ram the data memory is designed with 208 8 bits. the data memory is further divided into two functional groups, namely, special function registers (00h~2ah) and gen - eral purpose user data memory (30h~ffh). although most of them can be read or be written to, some are read only. the special function registers include an indirect ad - dressing register (r0:00h), memory pointer register (mp0:01h), accumulator (acc:05h), program counter lower-order byte register (pcl:06h), table pointer (tblp:07h), table higher-order byte register (tblh:08h), status register (status:0ah), interrupt control register 0 (intc:0bh), timer/event counter 0 (tmr0h:0ch,tmr0l:0dh), timer/event counter 0 control register (tmr0c:0eh), timer/event counter 1 (tmr1h:0fh, tmr1l:10h), timer/event counter 1 control register (tmr1c:11h), i/o registers (pa:12h,pb:14h), i/o control registers (pac:13h,pbc:15h), voice rom address latch0[23:0] (latch0h:18h, latch0m:19h, latch0l:1ah), voice rom address latch1[23:0] (latch1h:1bh, latch1m:1ch, latch1l:1dh), interrupt control reg - ister 1 (intch:1eh), table pointer higher-order byte register (tbhp:1fh), timer counter 3 (tmr3l:24h), timer counter 3 control register (tmr3c:25h), voice control register (voicec:26h), dac output (dah:27h,dal:28h), volume control register (vol:29h), voice rom latch data register (latchd:2ah). the general purpose data memory, addressed from 30h~ffh, is used for data and control information un - der instruction commands. the areas in the ram can directly handle the arithmetic, logic, increment, decrement, and rotate operations. ex - cept some dedicated bits, each bit in the ram can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through the memory pointer register 0 (mp0:01h) or the memory pointer register 1 (mp1:03h). address ram mapping read/write description 00h r0 r/w indirect addressing register 0 01h mp0 r/w memory pointer 0 02h r1 r/w indirect addressing register 1 03h mp1 r/w memory pointer 1 04h unused 05h acc r/w accumulator 06h pcl r/w program counter lower-order byte address 07h tblp r/w table pointer lower-order byte address 08h tblh r table higher-order byte content register 09h wdts r/w watchdog timer option setting register 0ah status r/w status register 0bh intc r/w interrupt control register 0 0ch tmr0h r/w timer/event counter 0 higher-byte register 0dh tmr0l r/w timer/event counter 0 lower-byte register 0eh tmr0c r/w timer/event counter 0 control register 0fh tmr1h r/w timer/event counter 1 higher-byte register 10h tmr1l r/w timer/event counter 1 lower-byte register 11h tmr1c r/w timer/event counter 1 control register 12h pa r/w port a i/o data register
HT86030/ht86070 rev. 1.00 11 february 20, 2006 address ram mapping read/write description 13h pac r/w port a i/o control register 14h pb r/w port b i/o data register 15h pbc r/w port b i/o control register 18h latch0h r/w voice rom address latch 0 [a23~a16] 19h latch0m r/w voice rom address latch 0 [a15~a8] 1ah latch0l r/w voice rom address latch 0 [a7~a0] 1bh latch1h r/w voice rom address latch 1 [a23~a16] 1ch latch1m r/w voice rom address latch 1 [a15~a8] 1dh latch1l r/w voice rom address latch 1 [a7~a0] 1eh intch r/w interrupt control register 1 1fh tbhp r/w table pointer higher-order byte register 23h unused 24h tmr3l r/w timer counter 3 lower-byte register 25h tmr3c r/w timer counter 3 control register 26h voicec r/w voice control register 27h dal r/w, higher-nibble available only dac output data d3~d0 to dal7~dal4 28h dah r/w dac output data d11~d4 to dah7~dah0 29h vol r/w, higher-nibble available only volume control register, and volume controlled by vol7~vol5 2ah latchd r voice rom data register 2bh~2fh unused 30h~ffh user data ram r/w user data ram indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1 (03h) respectively. reading lo - cation 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the ram by combining the corresponding indi - rect addressing registers. accumulator acc (05h) the accumulator (acc) is related to the alu opera - tions. it is also mapped to location 05h of the ram and is capable of operating with immediate data. the data movement between two data memory locations must pass through the acc. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions and provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz etc) status register status this 8-bit status register (0ah) consists of a zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), watchdog time-out flag (to). it also records the status information and controls the operation sequence. except the to and pdf flags, bits in the status register can be altered by instructions similar to other registers. data written into the status register does not alter the to or pdf flags. operations related to the status register,
HT86030/ht86070 rev. 1.00 12 february 20, 2006 however, may yield different results from those in - tended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the halt instruc - tion. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or executing the subroutine call, the status register will not be automati - cally pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. interrupts the HT86030/ht86070 provides an external interrupt, three 16-bit programmable timer interrupts, and an 8-bit programmable timer interrupt. the interrupt control reg - isters (intc:0bh, intch:1eh) contain the interrupt control bits to set to enable/disable and the interrupt re - quest flags. once an interrupt subroutine is serviced, all other inter - rupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the interrupt request flag is recorded. if a certain in - terrupt needs servicing within the service routine, the emi bit and the corresponding intc/intch bit may be set to allow interrupt nesting. if the stack is full, the inter- rupt request will not be acknowledged, even if the re- lated interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be pre- vented from becoming full. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at the specified location(s) in the program memory. only the program counter is pushed onto the stack. the programmer must save the contents of the register or status register (status) in advance if they are altered by an interrupt service pro - gram which corrupts the desired control sequence. external interrupt is triggered by a high-to-low/ low-to-high transition of int pin which sets the related interrupt request flag (eif:bit 4 of intc). when the inter - rupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (t0f:bit 5 of intc), caused by a timer/event counter 0 overflow. when the interrupt is enabled, and the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt re - quest flag (t0f) will be reset and the emi bit cleared to disable further interrupts. the internal timer/event counter 1 interrupt is initial - ized by setting the timer/event counter 1 interrupt re - quest flag (t1f:bit 6 of intc), caused by a timer/event counter 1 overflow. when the interrupt is enabled, and the stack is not full and the t1f bit is set, a subroutine call to location 0ch will occur. the related interrupt re - quest flag (t1f) will be reset and the emi bit cleared to disable further interrupts. the internal timer counter 3 interrupt is initialized by setting the timer counter 3 interrupt request flag (t3f:bit 1 of intch), caused by a timer counter 3 over- flow. when the interrupt is enabled, and the stack is not full and the t3f bit is set, a subroutine call to location 14h will occur. the related interrupt request flag (t3f) will be reset and the emi bit cleared to disable further in - terrupts. bit no. label function 0 c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1 ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. 3 ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5 to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register
HT86030/ht86070 rev. 1.00 13 february 20, 2006 during the execution of an interrupt subroutine, other in - terrupt acknowledges are held until the reti instruction is executed or the emi bit and the related interrupt con - trol bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, the ret or reti in - struction may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. the timer/event counter 0/1 interrupt request flag (t0f/t1f) which enables timer/event counter 0/1 con - trol bit (et0i/et1i), the timer counter 3 interrupt re - quest flag (t3f) which enables timer counter 3 control bit (et3i), and external interrupt request flag (eif) which enables external interrupt control bit (eei) form the interrupt control register (intc:0bh and intch:1eh). emi, eei, et0i, et1i and et3i are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt begin serviced. once the interrupt request flags (t0f, t1f, t3f, eif) are set, they will remain in the intc/intch register until the in - terrupts are serviced or cleared by a software instruc- tion. it is recommended that application programs do not use call subroutines within an interrupt subroutine. inter- rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt enable is not well con- trolled, once a call subroutine if used in the interrupt subroutine will corrupt the original control sequence. bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei controls the external interrupt (1= enabled; 0= disabled) 2 et0i controls the timer 0 interrupt (1= enabled; 0= disabled) 3 et1i controls the timer 1 interrupt (1= enabled; 0= disabled) 4 eif external interrupt request flag (1= active; 0= inactive) 5 t0f timer 0 request flag (1= active; 0= inactive) 6 t1f timer 1 request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc (0bh) register bit no. label function 0, 2~4, 6~7 unused bit, read as 0 1 et3i controls the timer 3 interrupt (1= enabled; 0= disabled) 5 t3f timer 3 interrupt request flag (1= active; 0= inactive) intch (1eh) 1 register interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch timer counter 3 overflow 4 14h oscillator configuration the HT86030/ht86070 provides two types of oscillator circuit for the system clock, i.e., rc oscillator and crystal oscillator. no matter what type of oscillator, the signal is used for the system clock. the halt mode stops the system oscillator and ignores external signal to con - serve power. if the rc oscillator is used, an external re - sistor between osc1 and vss is required, and the range of the resistance should be from 30k to 680k . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to synchronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscilla- tion may vary with vdd, temperature, and the chip itself due to process variations. it is therefore not suitable for timing sensitive operations where accurate oscillator frequency is desired. on the other hand, if the crystal oscillator is selected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two ex - ternal capacitors in osc1 and osc2 are required. "
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HT86030/ht86070 rev. 1.00 14 february 20, 2006 watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4), decided by mask options. this timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpre - dictable results. the watchdog timer can be disabled by mask option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with pe - riod 78 s normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approxi - mately 20 ms. this time-out period may vary with tem - perature, vdd and process variations. by invoking the wdt prescaler, longer time-out period can be realized. writing data to ws2, ws1, ws0 (bit 2,1,0 of wdts(09h)) can give different time-out period. if ws2, ws1, ws0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 sec - onds. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize a chip reset and set the status bit to . whereas in the halt mode, the overflow will initialize a warm re - set only the program counter and sp are reset to zero. to clear the contents of the wdt (including the wdt prescaler), three methods are adopted; external reset (external reset (a low level to res ), software instruc- tions, or a halt instruction. the software instruction is clr wdt and execution of the clr wdt instruc- tion will clear the wdt. ws2 ws1 ws0 division ratio 0 0 0 1:1 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts (09h) register power down halt the halt mode is initialized by a halt instruction and results in the following: the system oscillator will be turned off but the wdt os - cillator keeps running (if the wdt oscillator is selected). the contents of the on chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and recount again. all i/o ports maintain their their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . by examining the to and pdf flags, the reason for the chip reset can be determined. the pdf flag is cleared when the system powers-up or executes the clr wdt instruction, and is set when the halt instruction is executed. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and sp. the other maintain their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by a mask option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. if awakening from an interrupt, two se- quences may happen. if the related interrupt is disabled or the interrupt is enabled by the stack is full, the pro- gram will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. once a wake-up event occurs, it takes 1024 system clock period to resume normal operation. in other words, a dummy cycle period will be inserted after a wake-up. if the wake-up results from an interrupt ac - knowledge, the actual interrupt subroutine will be de - layed by one more cycle. if the wake-up results in next instruction execution, this will be executed immediately after a dummy period is finished. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be dis - abled. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. "
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HT86030/ht86070 rev. 1.00 15 february 20, 2006 reset there are 3 ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the program counter and sp, leav - ing the other circuits in their original state. some regis - ters remain unchanged during any other reset conditions. most registers are reset to their initial condi - tion when the reset conditions are met. by examining the pdf flag and to flag, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a halt state. when a system power up occurs, the sst delay is added during the reset period. but when the reset co- mes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. reset timing chart reset circuit reset configuration the function unit chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack timer/event counter 0/1 there are four timer counters are implemented in the HT86030/ht86070. the timer/event counter 0 and 1 contain 16-bit programmable count-up counters whose clock may come from an external source or the system clock divided by 4 (t1). using the internal instruction clock (t1), there is only one reference time base. the external clock input allows the user to count external events, measure time intervals or pulse width, or to gen- erate an accurate time base. there are three registers related to timer/event coun - ter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh). writing to tmr0l only writes the data into a low byte buffer. writing to tmr0h will write the data and the con - tents of the low byte buffer into the timer/event counter 0 preload register (16-bit) simultaneously. the timer/event counter 0 preload register is changed only by a write to tmr0h operation. writing to tmr0l will keep the timer/event counter 0 preload register un - changed. reading tmr0h will also latch the tmr0l into the low byte buffer to avoid false timing problems. reading the tmr0l only returns the value from the low byte buffer which may be a previously loaded value. in other words, the low byte of timer/event counter 0 cannot be read di - rectly. it must read the tmr0h first to ensure that the low byte contents of timer/event counter 0 are latched into the buffer.
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HT86030/ht86070 rev. 1.00 16 february 20, 2006 there are three registers related to the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). the timer/event counter 1 operates in the same man - ner as timer/event counter 0. bit no. label function 0~2, 5 unused bit, read as 0 3te to define the tmr0/tmr1 active edge of timer/event counter (0=active on low to high; 1=active on high to low) 4 ton to enable/disable timer counting (0=disabled; 1=enabled) 6 7 tm0, tm1 to define the operating mode (tmr1, tmr0) 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh)/tmr1c (11h) register the tmr0c is the timer/event counter 0 control regis - ter, which defines the timer/event counter 0 options. the timer/event counter 1 has the same options as the timer/event counter 0 and is defined by tmr1c. the timer/event counter control registers define the op- erating mode, counting enable or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which implies that the clock source comes from an ex- ternal pin. the timer mode functions as a normal timer with the clock source coming from the instruction clock. the pulse width measurement mode can be used to count the high or low level duration of an external signal (tmr0/tmr1). the counting method is based on the in - struction clock. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates a corresponding interrupt request flag (t0f/t1f; bit 5/6 of intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr0/tmr1 has re - ceived a transient from low to high (or high to low; if the te bit is 0) it will start counting until the tmr0/tmr1 re - turns to the original level and resets ton. the mea - sured result will remain in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be done. when ton is set again, the cycle measurement will function again as long as it receives further transient pulses. note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like in the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmr0c/tmr1c) should be set to 1. in the pulse width measurement mode, ton will be cleared automatically after the measurement cycle is complete. but in the other two modes ton can only be reset by in - struction. the overflow of the timer/event counter is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i/et1i can disable the corre- sponding interrupt service. in the case of a timer/event counter off condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. the timer/event counter will continue to operate until an overflow occurs. when the timer/event counter (reading tmr0h/ tmr1h) is read, the clock will be blocked to avoid er - rors. as this may result in a counting error, this must be taken into consideration by the programmer. "
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HT86030/ht86070 rev. 1.00 17 february 20, 2006 timer counter 3 the timer counter tmr3 is an 8-bit programmable count-up counter. its counting is as the same manner as timer event counter 0/1, but the clock source of tmr3 can be from internal instruction cycle (t1). the tmr3 is internal clock source only, i.e. (tm1,tm0)=(1,0). there is a 3-bit prescaler (tmr3s2,tmr3s1,tmr3s0) which defines different division ratio of tmr3 s clock source. bit no. label function 0~2 tmr3s2, tmr3s1, tmr3s0 to define the operating clock source (tmr3s2, tmr3s1, tmr3s0) 000: clock source/2 001: clock source/4 010: clock source/8 011: clock source/16 100: clock source/32 101: clock source/64 110: clock source/128 111: clock source/256 3te to define the tmr3 active edge of timer/event counter (0=active on low to high; 1=active on high to low) 4 ton to enable/disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 6 7 tm0, tm1 to define the operating mode (tm1, tm0) 01=unused 10=timer mode (internal clock) 11=unused 00=unused tmr3c (25h) register "
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HT86030/ht86070 rev. 1.00 18 february 20, 2006 the registers states are summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr0c xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr1c xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu latch0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0m xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1m xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu intch -000 ---0 -000 ---0 -000 ---0 -000 ---0 -uuu ---u tbhp ---x xxxx ---u uuuu ---u uuuu ---u uuuu ---u uuuu tmr3l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr3c xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx voicec 0--0 -00- u--u -uu- u--u -uu- u--u -uu- u--u -uu- dal xxxx ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu vol xxx- ---- uuu- ---- uuu- ---- uuu- ---- uuu- ---- latchd xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu note: u means unchanged x means unknown means undefined
HT86030/ht86070 rev. 1.00 19 february 20, 2006 input/output ports there are 16 bidirectional input/output lines in the microcontroller, labeled from pa to pb, which are mapped to the data memory of [12h] and [14h] respec - tively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a, [m] (m=12h or 14h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. to function as an input, the corresponding latch of the con - trol register must write 1 . the input source also de - pends on the control register. if the control register bit is 1 , the input will read the pad state. if the control regis - ter bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h and 15h. after a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h) in- structions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. the wake-up capability of port a is determined by mask option. there is a pull-high option available for all i/o lines. once the pull-high option is selected, all i/o lines have pull-high resistors. otherwise, the pull-high resistors are absent. it should be noted that a non-pull-high i/o line operating in input mode will cause a floating state. audio output and volume control dal, dah, vol the HT86030/ht86070 provides one 12-bit voltage type dac device for driving external 8 speaker through an external npn transistor. the programmer must write the voice data to register dal (27h) and dah (28h). the 12-bit audio output will be written to the higher nibble of dal and the whole byte of dah, and the dal3~0 is always read as 0h. there are 8 scales of vol - ume controllable level that are provided for the voltage type dac output. the programmer can change the vol - ume by only writing the volume control data to the higher-nibble of the vol (29h), and the lower-nibble of vol (29h) is always read as 0h. voice control register the voice control register controls the voice rom circuit and dac circuit, selects voice rom latch counter. if the dac circuit is not enabled, any dah/dal output is in- valid. writing a 1 to dac bit is to enable dac circuit, and writing a 0 to dac bit is to disable dac circuit. if the voice rom circuit is not enabled, then voice rom data cannot be accessed at all. writing a 1 to vromc bit is to enable the voice rom circuit, and writing a 0 to vromc bit is to disable the voice rom circuit. the bit 4 (latchc) is to determine what voice rom address latch counter will be adopted as voice rom address latch counter. d ( d d ( d
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HT86030/ht86070 rev. 1.00 20 february 20, 2006 voice rom data address latch counter latch0h(18h)/latch0m(19h)/latch0l(1ah), latch1h(1bh)/latch1m(1ch)/latch1l(1dh) and voice rom data register(2ah) the voice rom data address latch counter is the hand - shaking between the microcontroller and voice rom, where the voice codes are stored. one 8-bit of voice rom data will be addressed by setting 24-bit address latch counter latch0h/latch0m/latch0l or latch1h/latch1m/latch1l. after the 8-bit voice rom data is addressed, a few instruction cycles (4 sat least) will be cost to latch the voice rom data, then the microcontroller can read the voice data from latchd(2ah). example: read an 8-bit voice rom data which is lo - cated at address 000007h by address latch 0 set [26h].2 ; enable voice rom circuit clr [26h].4 ; select voice rom address ; latch counter 0 mov a, 07h ; mov latch0l, a ; set latch0l to 07h mov a, 00h ; mov latch0m, a ; set latch0m to 00h mov a, 00h ; mov latch0h, a ; set latch0h to 00h call delay time ; delay a short period of time mov a, latchd ; get voice data at 000007h bit no. label function 0, 3, 5~6 unused bit, read as 0 1 dac enable/disable dac circuit (0= disable dac circuit; 1= enable dac circuit) the dac circuit is not affected by the halt instruction. the software controls bit dac (voicec.1) whether to enable/disable. 2 vromc enable/disable voice rom circuit (0= disable voice rom circuit; 1= enable voice rom circuit) 4 latchc select voice rom counter (0= voice rom address latch 0; 1= voice rom address latch 1) voicec (26h) register mask option mask option description pa wake-up enable/disable pa wake-up function watchdog timer (wdt) enable/disable wdt function one or two clr instruction wdt clock source is from wdtosc or t1 external int trigger edge external int is triggered on falling edge only, or is triggered on falling and rising edge. external timer 0/1 clock source enable/disable external timer of timer 0 and timer 1. pa pull-high enable/disable pa pull-high pb pull-high enable/disable pb pull-high f osc r osc table (v dd =3v) f osc r osc 4mhz
10% 6mhz
10% 8mhz
10% 300k 200k 150k
application circuits HT86030/ht86070 rev. 1.00 21 february 20, 2006 4 - ( 7 4 ) . 9 ! ? : ! 3 ! 1 2 3 2 1 > ? : : ! ! * 1 : ? :
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package information 28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 HT86030/ht86070 rev. 1.00 22 february 20, 2006 4 - * ! 2 : g <
product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330
1 b reel inner diameter 62
1.5 c spindle hole diameter 13+0.5 0.2 d key slit width 2
0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2
0.2 HT86030/ht86070 rev. 1.00 23 february 20, 2006 ! 2
carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24
0.3 p cavity pitch 12
0.1 e perforation position 1.75
0.1 f cavity to perforation (width direction) 11.5
0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4
0.1 p1 cavity to perforation (length direction) 2
0.1 a0 cavity length 10.85
0.1 b0 cavity width 18.34
0.1 k0 cavity depth 2.97
0.1 t carrier tape thickness 0.35
0.01 c cover tape width 21.3 HT86030/ht86070 rev. 1.00 24 february 20, 2006 + :
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HT86030/ht86070 rev. 1.00 25 february 20, 2006 copyright 2006 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 43f, seg plaza, shen nan zhong road, shenzhen, china 518031 tel: 0755-8346-5589 fax: 0755-8346-5590 isdn: 0755-8346-5591 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holmate semiconductor, inc. (north america sales office) 46712 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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